memory array
英 [ˈmeməri əˈreɪ]
美 [ˈmeməri əˈreɪ]
网络 存储阵列; 内存数组; 内存阵列; 只读存储器阵列; 存储器阵列
双语例句
- However, the memory allocated for an array is based on its cardinality, and not on the maximum cardinality of its type.
然而，阵列的已分配内存是基于其基数的，而不是基于其类型的最大基数。 - Development of measurement system for radiation effect on static random access memory based field programmable gate array
静态随机访问存储器型现场可编程门阵列辐照效应测试系统研制 - In a memory cell array, a plurality of memory cells having ferroelectric capacitors amplifies the potential of the bit lines of each memory cell.
半导体存储装置。在存储单元阵列中设置具有铁电电容器的多个存储单元。多个检测放大器电路使各存储单元的位线的电位放大。 - Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。 - With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
与传统的全功能EEPROM相比，利用快闪存储器，整个存储器阵列或存储器的一部分的内容可在一个步骤中擦除。 - The called function allocates memory for the array.
被调用函数为该数组分配内存。 - EMC firstly applies FLASH chip solid state disk into the memory array, and unprecedentedly raises the performance and the energy efficiency.
EMC首次将FLASH芯片的固态硬盘运用于存储阵列，使其性能和能效获得前所未有的提升。 - It is shown that the two states ('0'and'1 ') of single-electron ring memory, which has a cyclic array of quantum dots, can be implemented by input voltage controlling the charges on the islands.
研究表明，单电子环形存储器单元电路利用量子点环状电路结构形式，由外接输入电压控制各岛上的电荷，能够得到存储器的“0”和“1”状态。 - A divided memory cell array architecture and high speed hierarchical sense amplifiers are employed in the design to optimize the structure of the circuit.
通过采用存储阵列的分块、敏感放大器的分级等技术，对电路的结构进行了优化。 - Logic Circuit With ROM Memory Array
用ROM存贮阵列构成逻辑电路 - Buffering High-Speed Packets with Tri-Stage Memory Array and Its Performance Analysis
基于三级存储阵列缓存高速数据包及性能分析 - This paper presents a tri-stage memory array architecture to solve the problem, which can accomplish the arbitrary high-speed packet buffer theoretically.
提出一种新型的三级存储阵列结构可以成功解决数据包存储器的容量和带宽问题，理论上可以实现任意高速数据包的缓存。 - Theoretical analysis of memory correlator convolver in diode array
二极管阵列结构存储相关卷积器的理论分析 - Method in Designing Program with Expanded Memory and Dealing with Large Array in Language C
C语言扩充存储器的编程技术及大数组的处理方法 - Designed and realized the data structure of disk array, how to organize the share memory of disk array.
设计并实现了用于存储磁盘阵列信息的内部数据结构，如何组织应用存储磁盘阵列各项信息的共享内存。 - A New Memory Array Structure Decreasing Disturb Between Memory Cells
一种减小存储单元间串扰的新型阵列布局结构 - Recently, researchers have paid more attention to Long Memory of financial time array.
最近，金融时间序列的长期记忆性行为引起了研究者们的广泛关注。 - This paper review elementary theory for new logic circuit with ROM memory array, and provide design method for two practical array logic circuit.
本文论述用ROM的存贮阵列构成新颖的组合逻辑电路和时序逻辑电路的基本原理，并给出两个实际的阵列式逻辑电路的设计方法。 - Some new technologies such as dividing the memory array into separated sub-arrays, ATD, pre-charge and balance, subsection decoding, multilevel sense amplifier, etc have been used.
设计中采用了诸如存储阵列分块技术，地址探测技术，预充电及平衡技术，分段译码技术，分级敏感放大器等一些新技术。 - Describes the bus topology architecture, memory array partitioning, command structure and command set, response structure, the read and write operation timings and the practical applications of the serial communication protocol of the Multi Media Card manufactured by Samsung Electronics.
介绍三星电子研发的多媒体存储卡的MMC串行通信协议的总线拓扑结构、存储体阵列分区、命令格式与命令集合、响应格式与响应意义以及各种读写操作时序和实际应用。 - Demand drives technical progress. Recently DRAM makes fast technical reform which including access speed increasing, memory capability increasing, cell array densify and cell cost down.
需求推动技术进步，近年来DRAM在存取速度的提升，记忆容量的增加，集成度及单位位元成本的降低等方面的技术革新速度都是非常快速的。 - In the memory array, the management and the monitoring module of the system, SCSI Enclosure Servers, brief name SES, have the graven function meaning.
在存储阵列中，系统的管理和监控模块&SCSI箱体服务（SCSIEnclosureServers，简称SES）模块起到的作用意义重大。 - The memory array consists of double ended read/ write memory cell.
存储阵列由具有采用双位线读，双位线写的存储单元构成。 - The built-in self repair system is given on the based of high-reliability built-in redundancy analysis strategy, the system is made of three mail parts: the embedded memory array, built-in self-test and high reliability built-in redundancy analysis.
在高可靠性内建冗余分析策略的基础上，实现了内建自修复系统，该系统主要由嵌入式存储器阵列、内建自测试和高可靠性内建冗余分析三个部分组成。 - When memory array segmentation is used, performance should be taken into consideration so that an optimum hierarchical structure can be achieved.
因此在进行存储阵列分割时应当评估其划分后的性能，以求获得最佳的符合设计要求的层次化结构。 - Advanced technologies, such as dynamic CMOS decoder which using SCL ( source-coupled-logic) circuits, pulse signal technology, latch type voltage sense amplifier, power gating, memory array segmentation are used in the design.
设计中采用了SCL（source-coupled-logic）结构的动态CMOS译码电路、脉冲信号技术、锁存型电压灵敏放大器、PowerGating、存储阵列分割等先进技术。 - However, memory array segmentation will lead to the increase of the chip area, as well as delay due to too much connection. So using memory array segmentation too much will cause the decrease of memory performance.
但存储阵列分割使整体芯片面积增大，同时带来了过多的互连线延时，过分的划分存储阵列可能使得eSRAM性能降低。 - As the control logic of the system, FPGA combines with Analog-to-Digital Converter ( ADC), serial-switched network, Flash memory array and the upper computer to form the entire system. 2) Using the top-down design method, the system is divided into several functional modules.
FPGA作为系统的控制逻辑，结合外围的模数转换器（ADC）、串行交换网络、Flash存储阵列和上位机，构建高速数据采集系统。2）按照自顶向下的设计方法，将系统划分为多个功能模块。 - Since the single ended read memory cell is adapted, the area of memory array is dramatically reduced. The total area of the register file is reduced to 0.01 mm2.
由于采用了单位线读存储单元，存储阵列的面积大大下降，整个寄存器文件的面积下降为0.01mm2。